dc.contributor | Universitat de Vic. Escola Politècnica Superior | |
dc.contributor | SPIE | |
dc.contributor.author | Serra i Serra, Moisès | |
dc.contributor.author | Martí i Puig, Pere | |
dc.contributor.author | Carrabina, Jordi | |
dc.date.accessioned | 2015-01-22T11:54:31Z | |
dc.date.available | 2015-01-22T11:54:31Z | |
dc.date.created | 2005 | |
dc.date.issued | 2005 | |
dc.identifier.citation | SERRA SERRA, Moisès; MARTI PUIG, Pere; CARRABINA, J. Rapid prototyping with the visual data environment of an OFDM WLAN system. Seville, SPAIN. BELLINGHAM; 1000 20TH ST, PO BOX 10, BELLINGHAM, WA 98227-0010 USA: SPIE-INT SOC OPTICAL ENGINEERING, 2005. | ca_ES |
dc.identifier.uri | http://hdl.handle.net/10854/3844 | |
dc.description.abstract | In this paper a rapid prototyping design flow is presented and applied to a prototype of the base-band physical
layer of a Hiperlan/2 WLAN transceiver. This physical layer is a high performance multi-rate system that
contains computationally intensive algorithms. A new method for prototyping the design flow and verifying the
process is to use the latest generation of system level design environments (visual data flow environment) for
DSPs. The System Generator and Matlab/Simulink tools form a visual data flow environment for FPGA allow
us to model DSP systems and explore algorithms. This environment also translates designs into hardware
implementations that are faithful, synthesizable and efficient, which can be explored and refined in rapid
prototyping platforms. | ca_ES |
dc.format | application/pdf | |
dc.format.extent | 6 p. | ca_ES |
dc.language.iso | eng | ca_ES |
dc.publisher | SPIE | ca_ES |
dc.rights | Tots els drets reservats | ca_ES |
dc.subject.other | Algorismes | ca_ES |
dc.title | Rapid prototyping with the visual data environment of an OFDM WLAN system | ca_ES |
dc.type | info:eu-repo/semantics/conferenceObject | ca_ES |
dc.identifier.doi | https://doi.org/10.1117/12.608847 | |
dc.rights.accessRights | info:eu-repo/semantics/closedAccess | ca_ES |